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Disambiguation of "Ohtake, Satoshi"

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Low-Cost Hardening of Image Processing Applications Against Soft Errors.

, , , , and . DFT, page 274-279. IEEE Computer Society, (2006)

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Satoshi Ejima

Satoshi Okawa

Satoshi Otomo

Satoshi Murayama

Satoshi Nishida

 

Other publications of authors with the same name

Delay Testing: Improving Test Quality and Avoiding Over-testing., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2011)A Method of Diagnostic Test Generation for Transition Faults., and . PRDC, page 273-278. IEEE Computer Society, (2015)A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency., , , and . Asian Test Symposium, page 306-311. IEEE Computer Society, (2005)Design for Testability Based on Single-Port-Change Delay Testing for Data Paths., , , and . Asian Test Symposium, page 254-259. IEEE Computer Society, (2005)A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification., , , and . VTS, page 71-76. IEEE Computer Society, (2009)Fast false path identification based on functional unsensitizability using RTL information., , , and . ASP-DAC, page 660-665. IEEE, (2009)Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation., , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 301-316. Springer, (2006)Factory Environment Monitoring: A Japanese Tea Manufacturer's Case., and . ICCE, page 1-3. IEEE, (2019)An approach to LFSR-based X-masking for built-in self-test., and . LATS, page 1-4. IEEE, (2017)Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability., , , and . IEICE Trans. Inf. Syst., 90-D (1): 296-305 (2007)