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New Techniques to Reduce the Execution Time of Functional Test Programs., , , and . IEEE Trans. Computers, 66 (7): 1268-1273 (2017)An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard., , , , , and . LATS, page 1-6. IEEE, (2017)The Use of Model Checking in ATPG for Sequential Circuits., , , and . CAV, volume 531 of Lecture Notes in Computer Science, page 86-95. Springer, (1990)New techniques for efficiently assessing reliability of SOCs., , , , and . Microelectron. J., 34 (1): 53-61 (2003)On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors., , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (4): 813-823 (2014)RT-Level ITC'99 Benchmarks and First ATPG Results., , and . IEEE Des. Test Comput., 17 (3): 44-53 (2000)System-level test bench generation in a co-design framework., , , , and . ETW, page 25-30. IEEE Computer Society, (2000)An experimental analysis of the effectiveness of the circular self-test path technique., , and . EURO-DAC, page 246-251. IEEE Computer Society, (1994)Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs., , , , and . J. Electron. Test., 23 (1): 47-54 (2007)GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (8): 991-1000 (1996)