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Disambiguation of "Wu, Ping-Chun"

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8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.

, , , , , , , , , , , , , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2304-2308 (April 2024)

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Ping Wu

Ping Wu

Shu-Chun Wu

Wei-Ping Wu

Ho-Chun Wu

 

Other publications of authors with the same name

8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips., , , , , , , , , and 11 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2304-2308 (April 2024)A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 58 (3): 877-892 (March 2023)A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices., , , , , , , , , and 10 other author(s). ISSCC, page 1-3. IEEE, (2022)16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips., , , , , , , , , and 11 other author(s). ISSCC, page 250-252. IEEE, (2021)Predictive Effects of the Quality of Online Peer-Feedback Provided and Received on Primary School Students' Quality of Question-Generation., and . J. Educ. Technol. Soc., 19 (3): 234-246 (2016)A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 59 (1): 196-207 (January 2024)Different identity revelation modes in an online peer-assessment learning environment: Effects on perceptions toward assessors, classroom climate and learning activities., and . Comput. Educ., 57 (3): 2167-2177 (2011)Challenges in Circuits of Nonvolatile Compute-In-Memory for Edge AI Chips., , , , , , and . MWSCAS, page 98-102. IEEE, (2023)A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating., , , , , , , , , and 7 other author(s). ISSCC, page 238-240. IEEE, (2021)A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices., , , , , , , , , and 7 other author(s). ISSCC, page 126-127. IEEE, (2023)