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A 256×256 14k range maps/s 3-D range-finding image sensor using row-parallel embedded binary.

, , and . ISSCC, page 404-405. IEEE, (2010)

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Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA., , and . ISLPED, page 3-8. IEEE/ACM, (2011)A 256×256 14k range maps/s 3-D range-finding image sensor using row-parallel embedded binary., , and . ISSCC, page 404-405. IEEE, (2010)Fully automated PLL compiler generating final GDS from specification., and . ISQED, page 437-442. IEEE, (2016)One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering Quantum Mechanical Effects., , and . VLSI Design, 6 (1-4): 65-67 (1998)A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation., , and . IEEE J. Solid State Circuits, 46 (11): 2500-2513 (2011)High-resolution measurement of magnetic field generated from cryptographic LSIs., , , , , and . SAS, page 111-114. IEEE, (2014)All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter., , , , and . ASP-DAC, page 79-80. IEEE, (2011)Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture., , and . ASP-DAC, page 323-324. IEEE, (1998)A smart position sensor for 3-D measurement., , , and . ASP-DAC, page 21-22. ACM, (2001)Pre-conditioning Free Footless DCVSL for High-performance Datapaths., , and . ICECS, page 1053-1056. IEEE, (2006)