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Mapping Large Scale Finite Element Computing on to Wafer-Scale Engines.

Y. Lin, R. Liang, Y. Li, H. Hu, and J. Hu. ASP-DAC, page 147-153. IEEE, (2022)

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Lin Lin

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Are Analytical Techniques Worthwhile for Analog IC Placement?Y. Lin, Y. Li, D. Fang, M. Madhusudan, S. Sapatnekar, R. Harjani, and J. Hu. DATE, page 154-159. IEEE, (2022)Mapping Large Scale Finite Element Computing on to Wafer-Scale Engines.Y. Lin, R. Liang, Y. Li, H. Hu, and J. Hu. ASP-DAC, page 147-153. IEEE, (2022)A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing.Y. Li, Y. Lin, M. Madhusudan, A. Sharma, S. Sapatnekar, R. Harjani, and J. Hu. MLCAD, page 1-6. IEEE, (2021)Machine Learning Techniques in Analog Layout Automation.T. Dhar, K. Kunal, Y. Li, Y. Lin, M. Madhusudan, J. Poojary, A. Sharma, S. Burns, R. Harjani, J. Hu and 3 other author(s). ISPD, page 71-72. ACM, (2021)MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs.Y. Lin, Y. Li, M. Madhusudan, S. Sapatnekar, R. Harjani, and J. Hu. MLCAD, page 1-6. IEEE, (2023)A Customized Graph Neural Network Model for Guiding Analog IC Placement.Y. Li, Y. Lin, M. Madhusudan, A. Sharma, W. Xu, S. Sapatnekar, R. Harjani, and J. Hu. ICCAD, page 135:1-135:9. IEEE, (2020)The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk).T. Dhar, K. Kunal, Y. Li, Y. Lin, M. Madhusudan, J. Poojary, A. Sharma, S. Burns, R. Harjani, J. Hu and 3 other author(s). ICCAD, page 54:1-54:2. IEEE, (2020)Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction.C. Chang, J. Pan, Z. Xie, Y. Li, Y. Lin, J. Hu, and Y. Chen. ASP-DAC, page 58-63. ACM, (2023)Exploring a Machine Learning Approach to Performance Driven Analog IC Placement.Y. Li, Y. Lin, M. Madhusudan, A. Sharma, W. Xu, S. Sapatnekar, R. Harjani, and J. Hu. ISVLSI, page 24-29. IEEE, (2020)Performance-driven Wire Sizing for Analog Integrated Circuits.Y. Li, Y. Lin, M. Madhusudan, A. Sharma, S. Sapatnekar, R. Harjani, and J. Hu. ACM Trans. Design Autom. Electr. Syst., 28 (2): 19:1-19:23 (March 2023)

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Disambiguation of "Lin, Yishuang"

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Mapping Large Scale Finite Element Computing on to Wafer-Scale Engines.

Please choose a person to relate this publication to

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lin, Yishuang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Mapping Large Scale Finite Element Computing on to Wafer-Scale Engines.

Please choose a person to relate this publication to

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

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URL
DOI
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Chicago
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Mapping Large Scale Finite Element Computing on to Wafer-Scale Engines.