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False-Noise Analysis using Logic Implications., , , , , and . ICCAD, page 515-. IEEE Computer Society, (2001)Library-less synthesis for static CMOS combinational logic circuits., , , , , , , and . ICCAD, page 658-662. IEEE Computer Society / ACM, (1997)Fast power loss calculation for digital static CMOS circuits., , , , , and . ED&TC, page 411-415. IEEE Computer Society, (1997)False-Noise Analysis Using Resolution Method., , , , , and . ISQED, page 437-442. IEEE Computer Society, (2002)False-noise analysis using logic implications., , , and . ACM Trans. Design Autom. Electr. Syst., 7 (3): 474-498 (2002)False-Noise Analysis for Domino Circuits., , , , , and . DATE, page 784-789. IEEE Computer Society, (2004)SOI Transistor Model for Fast Transient Simulation., , , , , , , , , and . ICCAD, page 120128. IEEE Computer Society / ACM, (2003)Delay noise pessimism reduction by logic correlations., , , , , , and . ICCAD, page 160-167. IEEE Computer Society / ACM, (2004)Transistor reordering for low power CMOS gates using an SP-BDD representation., , and . ISLPD, page 161-166. ACM, (1995)Calculation of stress probability for NBTI-aware timing analysis., , and . ISQED, page 714-718. IEEE Computer Society, (2009)