Author of the publication

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults.

, , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2938-2951 (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications., , , , , , and . IEEE Trans. Aerosp. Electron. Syst., 56 (4): 2666-2676 (2020)CC-RTSV: Cross-Cellular Based Redundant TSV Design for 3D ICs., , , , , , , and . J. Circuits Syst. Comput., 29 (11): 2050144:1-2050144:19 (2020)A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications., , , , , , and . Integr., (2022)Valid test pattern identification for VLSI adaptive test., , , and . Integr., (2022)Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications., , , , , , , , and . IEEE Trans. Aerosp. Electron. Syst., 58 (1): 517-529 (2022)Method of generating strategic guidance information for driving evacuation flows to approach safety-based system optimal dynamic flows: Case study of a large stadium., , , , and . J. Systems Science & Complexity, 28 (3): 606-622 (2015)A high performance SEU-tolerant latch for nanoscale CMOS technology.. DATE, page 1-5. European Design and Automation Association, (2014)A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells., , , , , , , , and . ITC-Asia, page 139-144. IEEE, (2019)Design of Wireless Network on Chip with Priority-Based MAC., , , , , and . Journal of Circuits, Systems, and Computers, 28 (8): 1950124:1-1950124:18 (2019)Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS., , , , and . Microelectron. J., (2017)