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Constraint centric scheduling guide., , , , and . SIGARCH Comput. Archit. News, 41 (2): 17-21 (2013)Heterogeneous Von Neumann/dataflow microprocessors., , and . Commun. ACM, 62 (6): 83-91 (2019)MapReduce for the Cell Broadband Engine Architecture., and . IBM J. Res. Dev., 53 (5): 10 (2009)ISA Wars: Understanding the Relevance of ISA being RISC or CISC to Performance, Power, and Energy on Modern Architectures., , , and . ACM Trans. Comput. Syst., 33 (1): 3:1-3:34 (2015)Kickstarting Semiconductor Innovation with Open Source Hardware., , , and . Computer, 50 (6): 50-59 (2017)Pagerank Computation and Keyword Search on Distributed Systems and P2P Networks., , , and . J. Grid Comput., 1 (3): 291-307 (2003)Toward a multicore architecture for real-time ray-tracing., , , , and . MICRO, page 176-187. IEEE Computer Society, (2008)Universal Mechanisms for Data-Parallel Architectures., , , and . MICRO, page 303-314. IEEE Computer Society, (2003)A Scheduling Framework for Spatial Architectures Across Multiple Constraint-Solving Theories., , , , , and . ACM Trans. Program. Lang. Syst., 37 (1): 2:1-2:30 (2014)Applying Hardware Transactional Memory for Concurrency-Bug Failure Recovery in Production Runs., , , and . USENIX Annual Technical Conference, page 837-850. USENIX Association, (2018)