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Scaling Reverse Time Migration Performance through Reconfigurable Dataflow Engines.

, , , , , , , , and . IEEE Micro, 34 (1): 30-40 (2014)

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A highly-efficient and green data flow engine for solving euler atmospheric equations., , , , , , , and . FPL, page 1-6. IEEE, (2014)Custom Hardware Architectures for Posture Analysis., , , , , , and . FPT, page 77-84. IEEE, (2005)Surviving the end of frequency scaling with reconfigurable dataflow computing., and . SIGARCH Comput. Archit. News, 39 (4): 60-65 (2011)Dynamic clock-frequencies for FPGAs., , , , and . Microprocess. Microsystems, 30 (6): 388-397 (2006)Designing a Posture Analysis System with Hardware Implementation., , , , , , and . J. VLSI Signal Process., 47 (1): 33-45 (2007)CHIPS: Custom Hardware Instruction Processor Synthesis., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (3): 528-541 (2008)Evaluating Sampling Based Hotspot Detection., and . ARCS, volume 5455 of Lecture Notes in Computer Science, page 28-39. Springer, (2009)HAGAR: Efficient Multi-context Graph Processors., , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 915-924. Springer, (2002)Towards optimal custom instruction processors., , , and . Hot Chips Symposium, page 1-23. IEEE, (2006)Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs., , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 364-373. Springer, (2004)