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A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.

A. Varzaghani, B. Bozorgzadeh, J. Lam, A. Goel, X. Yuan, M. Elzeftawi, M. Izad, S. Sarkar, A. Baldisserotto, S. Ryu, S. Mikes, J. Hwang, V. Joshi, S. Naraghi, D. Kadia, M. Ranjbar, P. Lee, D. Loizos, S. Zogopoulos, S. Verma, and S. Sidiropoulos. VLSI Technology and Circuits, page 26-27. IEEE, (2022)

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Aida Nonn

Experimentelle und numerische Analyse des Schädigungsverhaltens von HybridlaserschweiverbindungenA. Nonn. TU Aachen, (2009)

Patricia Woedem Aidam

Aida Zewdu Kebede

Mu ammad aidar - bkan r

Ibr al- aidar

Other publications of authors with the same name

A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration.A. Varzaghani, and C. Yang. IEEE J. Solid State Circuits, 41 (2): 310-319 (2006)A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE.A. Emami-Neyestanak, A. Varzaghani, J. Bulzacchelli, A. Rylyakov, C. Yang, and D. Friedman. IEEE J. Solid State Circuits, 42 (4): 889-896 (2007)A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter.A. Varzaghani, and C. Yang. IEEE J. Solid State Circuits, 41 (4): 935-944 (2006)A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS.B. Raghavan, A. Varzaghani, L. Rao, H. Park, X. Yang, Z. Huang, Y. Chen, R. Kattamuri, C. Wu, B. Zhang and 3 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A 10.3GS/s 6b flash ADC for 10G Ethernet applications.S. Verma, A. Kasapi, L. min Lee, D. Liu, D. Loizos, S. Paik, A. Varzaghani, S. Zogopoulos, and S. Sidiropoulos. ISSCC, page 462-463. IEEE, (2013)A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications.A. Varzaghani, A. Kasapi, D. Loizos, S. Paik, S. Verma, S. Zogopoulos, and S. Sidiropoulos. IEEE J. Solid State Circuits, 48 (12): 3038-3048 (2013)A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization.A. Varzaghani, and C. Yang. IEEE J. Solid State Circuits, 44 (3): 901-915 (2009)A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.A. Varzaghani, B. Bozorgzadeh, J. Lam, A. Goel, X. Yuan, M. Elzeftawi, M. Izad, S. Sarkar, A. Baldisserotto, S. Ryu and 11 other author(s). VLSI Technology and Circuits, page 26-27. IEEE, (2022)

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Disambiguation of "Varzaghani, Aida"

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A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.

Please choose a person to relate this publication to

Aida Nonn

Patricia Woedem Aidam

Aida Zewdu Kebede

Mu ammad aidar - bkan r

Ibr al- aidar

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Varzaghani, Aida"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.

Please choose a person to relate this publication to

Aida Nonn

Patricia Woedem Aidam

Aida Zewdu Kebede

Mu ammad aidar - bkan r

Ibr al- aidar

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.