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A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.

A. Varzaghani, B. Bozorgzadeh, J. Lam, A. Goel, X. Yuan, M. Elzeftawi, M. Izad, S. Sarkar, A. Baldisserotto, S. Ryu, S. Mikes, J. Hwang, V. Joshi, S. Naraghi, D. Kadia, M. Ranjbar, P. Lee, D. Loizos, S. Zogopoulos, S. Verma, and S. Sidiropoulos. VLSI Technology and Circuits, page 26-27. IEEE, (2022)

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Mohamed Mohamed

Mohamed Mohamed Halawa

Mohamed Mohamed Gibry

Mohamed Samer Mohamed

Mohamed Ali Mohamed

Other publications of authors with the same name

A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET.Y. Frans, M. Elzeftawi, H. Hedayati, J. Im, V. Kireev, T. Pham, J. Shin, P. Upadhyaya, L. Zhou, S. Asuncion and 4 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET.Y. Frans, S. McLeod, H. Hedayati, M. Elzeftawi, J. Namkoong, W. Lin, J. Im, P. Upadhyaya, and K. Chang. ISSCC, page 68-70. IEEE, (2016)A 1.3µW 0.0075mm2 neural amplifier and capacitor-integrated electrodes for high density neural implant recording.M. Elzeftawi, S. Beach, L. Wang, and L. Theogarajan. BioCAS, page 236-239. IEEE, (2012)A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process.A. Jose, V. Abramzon, M. Elzeftawi, M. Wang, K. Kim, Y. Song, S. Moballegh, J. Kamali, and A. Amirkhany. CICC, page 1-4. IEEE, (2019)10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS.A. Elkholy, A. Elmallah, M. Elzeftawi, K. Chang, and P. Hanumolu. ISSCC, page 192-193. IEEE, (2016)A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET.Y. Frans, J. Shin, L. Zhou, P. Upadhyaya, J. Im, V. Kireev, M. Elzeftawi, H. Hedayati, T. Pham, S. Asuncion and 4 other author(s). IEEE J. Solid State Circuits, 52 (4): 1101-1110 (2017)A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET.Y. Frans, S. McLeod, H. Hedayati, M. Elzeftawi, J. Namkoong, W. Lin, J. Im, P. Upadhyaya, and K. Chang. IEEE J. Solid State Circuits, 51 (12): 3167-3177 (2016)A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.A. Varzaghani, B. Bozorgzadeh, J. Lam, A. Goel, X. Yuan, M. Elzeftawi, M. Izad, S. Sarkar, A. Baldisserotto, S. Ryu and 11 other author(s). VLSI Technology and Circuits, page 26-27. IEEE, (2022)

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Disambiguation of "Elzeftawi, Mohamed"

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A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.

Please choose a person to relate this publication to

Mohamed Mohamed

Mohamed Mohamed Halawa

Mohamed Mohamed Gibry

Mohamed Samer Mohamed

Mohamed Ali Mohamed

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Elzeftawi, Mohamed"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.

Please choose a person to relate this publication to

Mohamed Mohamed

Mohamed Mohamed Halawa

Mohamed Mohamed Gibry

Mohamed Samer Mohamed

Mohamed Ali Mohamed

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.