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Disambiguation of "Lee, Chia-Fu"

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Recent Progress and Next Directions for Embedded MRAM Technology.

, , , , , , , , , , , , , , and . VLSI Circuits, page 190-. IEEE, (2019)

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Chia-Lin Lee

Shu-Chia Lee

Chia-shun Lee

Pin-Chia Lee

Wei Chia Lee

 

Other publications of authors with the same name

A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations., , , , , , , , , and 8 other author(s). ISSCC, page 1-3. IEEE, (2022)5G Radio Access Network Design with the Fog Paradigm: Confluence of Communications and Computing., , , , , , and . IEEE Communications Magazine, 55 (4): 46-52 (2017)A 55-nm, 0.86-Volt operation, 75MHz high speed, 96uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash., , , , , , , , , and 3 other author(s). VLSI-DAT, page 1-4. IEEE, (2013)A 4nm 6163-TOPS/W/b $4790-TOPS/mm^2/b$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update., , , , , , , , , and 8 other author(s). ISSCC, page 132-133. IEEE, (2023)A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application., , , , and . A-SSCC, page 9-12. IEEE, (2017)A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications., , , , , , , , and . VLSI Technology and Circuits, page 24-25. IEEE, (2022)A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity., , , , , , , , , and 8 other author(s). ISSCC, page 494-495. IEEE, (2023)34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell., , , , , , , , , and 13 other author(s). ISSCC, page 572-574. IEEE, (2024)Recent Progress and Next Directions for Embedded MRAM Technology., , , , , , , , , and 5 other author(s). VLSI Circuits, page 190-. IEEE, (2019)Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 54 (4): 1029-1038 (2019)