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Using configurable computing to accelerate Boolean satisfiability.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (6): 861-868 (1999)

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Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability., , , and . DAC, page 194-199. ACM Press, (1998)Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements using SystemC., and . ICCD, page 502-504. IEEE Computer Society, (2004)Adaptive Analog-to-Digital Converter Platform for Mixed-Signal System-on-Chip., and . ESA, page 69-73. CSREA Press, (2005)Using configurable computing to accelerate Boolean satisfiability., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (6): 861-868 (1999)An Architectural Power Estimator for Analog-to-Digital Converters., and . ICCD, page 397-400. IEEE Computer Society, (2004)Accelerating Boolean Satisfiability with Configurable Hardware., , , and . FCCM, page 186-195. IEEE Computer Society, (1998)A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models., and . ACM Great Lakes Symposium on VLSI, page 341-344. ACM, (2006)Solving Boolean Satisfiability with Dynamic Hardware Configurations., , , and . FPL, volume 1482 of Lecture Notes in Computer Science, page 326-335. Springer, (1998)A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models., and . ICCD, page 383-388. IEEE, (2006)