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Using configurable computing to accelerate Boolean satisfiability.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (6): 861-868 (1999)

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Certified Timing Verification and the Transition Delay of a Logic Circuit., , , and . DAC, page 549-555. IEEE Computer Society Press, (1992)Exploiting Retiming in a Guided Simulation Based Validation Methodology., , and . CHARME, volume 1703 of Lecture Notes in Computer Science, page 350-353. Springer, (1999)On Solving the Partial MAX-SAT Problem., and . SAT, volume 4121 of Lecture Notes in Computer Science, page 252-265. Springer, (2006)A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors., and . The Compiler Design Handbook, 2nd ed., CRC Press, (2007)Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation., and . CP, volume 2470 of Lecture Notes in Computer Science, page 200-215. Springer, (2002)Specification and encoding of transaction interaction properties., , and . Formal Methods Syst. Des., 39 (2): 144-164 (2011)System Level Design: Orthogonolization of Concerns and Platform-Based Design, , , , and . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (December 2000)Retiming and resynthesis: optimizing sequential networks with combinational techniques., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (1): 74-84 (1991)Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (5): 568-578 (1993)PPU: A Control Error-Tolerant Processor for Streaming Applications with Formal Guarantees., , , , and . ACM J. Emerg. Technol. Comput. Syst., 13 (3): 43:1-43:29 (2017)