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DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads.

P. Gu, X. Xie, S. Li, D. Niu, H. Zheng, K. Malladi, and Y. Xie. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (8): 1586-1599 (2021)

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Jier Niu

Heinrich Dimingen

Chaowei Niu

Xinyu Niu

Wenjun Niu

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3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code.Q. Zou, D. Niu, Y. Cao, and Y. Xie. ASP-DAC, page 762-767. IEEE, (2014)Design of cross-point metal-oxide ReRAM emphasizing reliability and cost.D. Niu, C. Xu, N. Muralimanohar, N. Jouppi, and Y. Xie. ICCAD, page 17-23. IEEE, (2013)Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network.L. Huang, Z. Zhang, S. Li, D. Niu, Y. Guan, H. Zheng, and Y. Xie. IEEE Access, (2022)MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing.X. Xie, P. Gu, Y. Ding, D. Niu, H. Zheng, and Y. Xie. ACM Trans. Archit. Code Optim., 20 (3): 40:1-40:26 (September 2023)OpSparse: a Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs.Z. Du, Y. Guan, T. Guan, D. Niu, L. Huang, H. Zheng, and Y. Xie. CoRR, (2022)COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning.H. Zhu, B. Jiao, J. Zhang, X. Jia, Y. Wang, T. Guan, S. Wang, D. Niu, H. Zheng, C. Chen and 6 other author(s). ISSCC, page 1-3. IEEE, (2022)A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.G. Sun, Y. Joo, Y. Chen, D. Niu, Y. Xie, Y. Chen, and H. Li. HPCA, page 1-12. IEEE Computer Society, (2010)Low power memristor-based ReRAM design with Error Correcting Code.D. Niu, Y. Xiao, and Y. Xie. ASP-DAC, page 79-84. IEEE, (2012)STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization.F. Wang, G. Luo, G. Sun, J. Zhang, J. Kang, Y. Wang, D. Niu, and H. Zheng. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (5): 864-877 (2021)Overcoming the challenges of crossbar resistive memory architectures.C. Xu, D. Niu, N. Muralimanohar, R. Balasubramonian, T. Zhang, S. Yu, and Y. Xie. HPCA, page 476-488. IEEE Computer Society, (2015)

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Disambiguation of "Niu, Dimin"

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DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads.

Please choose a person to relate this publication to

Jier Niu

Heinrich Dimingen

Chaowei Niu

Xinyu Niu

Wenjun Niu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Niu, Dimin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads.

Please choose a person to relate this publication to

Jier Niu

Heinrich Dimingen

Chaowei Niu

Xinyu Niu

Wenjun Niu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads.