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An FPGA sliding window-based architecture harris corner detector., , и . FPL, стр. 1-4. IEEE, (2014)Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment., , , , и . DSD, стр. 634-640. IEEE Computer Society, (2007)Quantum circuit's reliability assessment with VHDL-based simulated fault injection., , , и . Microelectron. Reliab., 50 (2): 304-311 (2010)Layered LDPC decoder in-order message access scheduling: a case study., и . SACI, стр. 193-198. IEEE, (2020)Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques., , и . DDECS, стр. 149-152. IEEE Computer Society, (2015)Direct FPGA-based power profiling for a RISC processor., , , , , , , , и . I2MTC, стр. 1578-1583. IEEE, (2015)Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding., , и . DSD, стр. 104-109. IEEE Computer Society, (2018)Generation of floating point 2D translation operators for FPGA., , и . SACI, стр. 289-294. IEEE, (2015)Template-based QC-LDPC decoder architecture generation., , и . ICICS, стр. 1-5. IEEE, (2015)Automatic Generation of FPGA Hardware Accelerators for Graphics Applications., и . PECCS, стр. 383-386. SciTePress, (2012)