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Disambiguation of "Luo, Guojie"

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MEC: An Open-source Fine-grained Mapping Equivalence Checking Tool for FPGA.

, , , , , , , , and . CoRR, (2023)

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Yongxiang Luo

Jia Luo

Xiaoguang Luo

Junfeng Luo

Quan Luo

 

Other publications of authors with the same name

Floorplanning challenges in early chip planning., , , , , , and . SoCC, page 388-393. IEEE, (2011)Physical hierarchy exploration of 3D processors.. ISOCC, page 139-141. IEEE, (2011)An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (4): 510-523 (2013)FPGA Acceleration for 3-D Low-Dose Tomographic Reconstruction., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (4): 666-679 (2021)Combining Static and Dynamic Load Balance in Parallel Routing for FPGAs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (9): 1850-1863 (2021)Area Efficient Pattern Representation of Binary Neural Networks on RRAM., , , , , and . J. Comput. Sci. Technol., 36 (5): 1155-1166 (2021)OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit., , , , , and . ASICON, page 1-4. IEEE, (2023)SSR: A Skeleton-based Synthesis Flow for Hybrid Processing-in-RRAM Modes., , and . ICCAD, page 1-9. IEEE, (2021)FPGA-Based Real-Time Super-Resolution System for Ultra High Definition Videos., , , , and . FCCM, page 181-188. IEEE Computer Society, (2018)Scaling Up Physical Design: Challenges and Opportunities., , , and . ISPD, page 131-137. ACM, (2016)