( en | de | ru )

 

Disambiguation of "Nath, Siddhartha"

Author of the publication

copydeleteadd this publication to your clipboard
A deep learning methodology to proliferate golden signoff timing.

, , , and . DATE, page 1-6. European Design and Automation Association, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Siddhartha Chattopadhyay

Siddhartha Roy

Siddhartha Kargupta

Siddhartha Schwenzer

Siddhartha Chib

 

Other publications of authors with the same name

Redefining the Role of the CPU in the Era of CPU-GPU Integration., , , , and . IEEE Micro, 32 (6): 4-16 (2012)BufFormer: A Generative ML Framework for Scalable Buffering., , , , and . ASP-DAC, page 264-270. ACM, (2023)Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes., and . ISPD, page 83-90. ACM, (2021)Generative self-supervised learning for gate sizing: invited., , , , , and . DAC, page 1331-1334. ACM, (2022)Optimal reliability-constrained overdrive frequency selection in multicore systems., and . ISQED, page 300-308. IEEE, (2014)A Fast Learning-Driven Signoff Power Optimization Framework., , , and . ICCAD, page 161:1-161:9. IEEE, (2020)TransSizer: A Novel Transformer-Based Fast Gate Sizer., , , , , and . ICCAD, page 74:1-74:9. ACM, (2022)Incremental multiple-scan chain ordering for ECO flip-flop insertion., , and . ICCAD, page 705-712. IEEE, (2013)The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap., , , and . ICCD, page 153-160. IEEE Computer Society, (2014)RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning., , , and . DAC, page 733-738. IEEE, (2021)