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Controllability of multi-level states in memristive device models using a transistor as current compliance during SET operation., , , and . IJCNN, page 1-8. IEEE, (2015)A Complementary Resistive Switch-Based Crossbar Array Adder., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (1): 64-74 (2015)Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays., , , , and . ACM J. Emerg. Technol. Comput. Syst., 14 (2): 30:1-30:14 (2018)Applicability of Well-Established Memristive Models for Simulations of Resistive Switching Devices., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (8): 2402-2410 (2014)Memristive Device Modeling and Circuit Design Exploration for Computation-in-Memory., , , and . ISCAS, page 1-5. IEEE, (2019)Memory Devices: Energy-Space-Time Tradeoffs., , , , , , , and . Proc. IEEE, 98 (12): 2185-2200 (2010)The influence of interfacial (sub)oxide layers on the properties of pristine resistive switching devices., , , , , and . NVMTS, page 1-4. IEEE, (2018)2022 roadmap on neuromorphic computing and engineering., , , , , , , , , and 49 other author(s). Neuromorph. Comput. Eng., 2 (2): 22501 (2022)A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs., , , , , , , , , and 1 other author(s). ACM J. Emerg. Technol. Comput. Syst., 18 (2): 32:1-32:25 (2022)A Study of the Electroforming Process in 1T1R Memory Arrays., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (2): 558-568 (February 2023)