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A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.

, , , , , , , and . IEEE J. Solid State Circuits, 59 (4): 1158-1170 (April 2024)

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Complexity in an Industrial flyback converter., , , and . Journal of Circuits, Systems, and Computers, 5 (4): 627-634 (1995)A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF., , , and . IEEE J. Solid State Circuits, 49 (2): 405-415 (2014)Editorial: Where Are We Now and Where Do We Go From Here.. IEEE Open J. Circuits Syst., (2022)Guest Editorial Special Section on 2010 IEEE Custom Integrated Circuits Conference (CICC 2010)., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (9): 1993-1995 (2011)Guest Editorial Special Issue on ISCAS 2010., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (7): 1457 (2011)Progress update and a look ahead.. IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (1): 1-2 (2013)A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration., , , and . CICC, page 317-320. IEEE, (2007)A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizer., , and . CICC, page 429-432. IEEE, (2003)Cellular neural networks to explore complexity., , , and . Soft Comput., 1 (3): 120-136 (1997)Two-path band-pass Δ∑ modulator with 40-MHz IF 72-dB DR at 1-MHz bandwidth consuming 16 mW., , , , and . ESSCIRC, page 248-251. IEEE, (2007)