Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.

R. Mittal, H. Shibata, S. Patil, E. Krommenhoek, P. Shrestha, G. Manganaro, A. Chandrakasan, and H. Lee. IEEE J. Solid State Circuits, 59 (4): 1158-1170 (April 2024)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hajime Sakai

Daisuke Shibata

Tomohiro Shibata

Hajime Konno

Hajime Myoken

Other publications of authors with the same name

15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS.Y. Dong, J. Zhao, W. Yang, T. Caldwell, H. Shibata, R. Schreier, Q. Meng, J. Silva, D. Paterson, and J. Gealow. ISSCC, page 278-279. IEEE, (2016)Measurement System for Switching Current Distribution in Intrinsic Josephson Junctions.H. Kashiwaya, T. Matsumoto, H. Shibata, K. Tani, and S. Kashiwaya. IEICE Trans. Electron., 90-C (3): 605-606 (2007)A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers.Q. Wang, H. Shibata, A. Liscidini, and A. Carusone. IEEE J. Solid State Circuits, 53 (3): 681-691 (2018)A -89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique.J. Zhao, Y. Dong, W. Yang, H. Shibata, P. Shrestha, Z. Li, T. Caldwell, J. Silva, and J. Gealow. IEEE Trans. Circuits Syst. II Express Briefs, 65-II (7): 859-863 (2018)A 375mW Quadrature Bandpass ΔΣ ADC with 90dB DR and 8.5MHz BW at 44MHz.R. Schreier, N. Abaskharoun, H. Shibata, I. Mehr, S. Rose, and D. Paterson. ISSCC, page 141-150. IEEE, (2006)A 100mW 10MHz-BW CT ΔΣ Modulator with 87dB DR and 91dBc IMD.W. Yang, W. Schofield, H. Shibata, S. Korrapati, A. Shaikh, N. Abaskharoun, and D. Ribner. ISSCC, page 498-499. IEEE, (2008)Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS.Y. Dong, J. Silva, Q. Meng, J. Zhao, W. Yang, T. Caldwell, H. Shibata, Z. Li, D. Paterson, and J. Gealow. CICC, page 1-4. IEEE, (2017)Advances in high-speed continuous-time delta-sigma modulators.T. Caldwell, D. Alldred, R. Schreier, H. Shibata, and Y. Dong. CICC, page 1-8. IEEE, (2014)Analog circuit synthesis by superimposing of sub-circuits.H. Shibata, and N. Fujii. ISCAS (5), page 427-430. IEEE, (2001)A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD.H. Shibata, V. Kozlov, Z. Ji, A. Ganesan, H. Zhu, D. Paterson, J. Zhao, S. Patil, and S. Pavan. IEEE J. Solid State Circuits, 52 (12): 3219-3234 (2017)

BibSonomy

Disambiguation of "Shibata, Hajime"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.

Please choose a person to relate this publication to

Hajime Sakai

Daisuke Shibata

Tomohiro Shibata

Hajime Konno

Hajime Myoken

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Shibata, Hajime"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.

Please choose a person to relate this publication to

Hajime Sakai

Daisuke Shibata

Tomohiro Shibata

Hajime Konno

Hajime Myoken

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.