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Disambiguation of "Moretó, Miquel"

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Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86.

, , , , , and . Future Gener. Comput. Syst., (2020)

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Núria Gel Moretó

Miguel Moreto

Beate Miquel

Miquel Marqués

Joan Miquel

 

Other publications of authors with the same name

Adaptive Power Shifting for Power-Constrained Heterogeneous Systems., , , , , , and . IEEE Trans. Computers, 72 (3): 627-640 (March 2023)Dynamic Cache Partitioning Based on the MLP of Cache Misses., , , and . Trans. High Perform. Embed. Archit. Compil., (2011)A Security Model for Randomization-based Protected Caches., , , , and . IACR Cryptol. ePrint Arch., (2022)Functional Verification of a RISC-V Vector Accelerator., , , , , , , , , and 2 other author(s). IEEE Des. Test, 40 (3): 36-44 (June 2023)Runtime-assisted cache coherence deactivation in task parallel programs., , , , and . SC, page 35:1-35:12. IEEE / ACM, (2018)CPU Accounting in CMP Processors., , , , , and . IEEE Comput. Archit. Lett., 8 (1): 17-20 (2009)On the use of many-core Marvell ThunderX2 processor for HPC workloads., , , and . J. Supercomput., 77 (4): 3315-3338 (2021)Evaluating Execution Time Predictability of Task-Based Programs on Multi-Core Processors., , , , and . Euro-Par Workshops (2), volume 8806 of Lecture Notes in Computer Science, page 218-229. Springer, (2014)SafeSU: an Extended Statistics Unit for Multicore Timing Interference., , , , , , , and . ETS, page 1-4. IEEE, (2021)Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs., , , , , , , , , and . DATE, page 628-631. IEEE, (2022)