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Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86.

, , , , , and . Future Gener. Comput. Syst., (2020)

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Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors., , and . Computer, 20 (7): 77-89 (1987)Errata on "Measuring Experimental Error in Microprocessor Simulation"., , , , , , and . SIGARCH Comput. Archit. News, 30 (1): 2-4 (2002)Picos: A hardware runtime architecture support for OmpSs., , , , and . Future Gener. Comput. Syst., (2015)Register Constrained Modulo Scheduling., , , and . IEEE Trans. Parallel Distributed Syst., 15 (5): 417-430 (2004)CPU Accounting in CMP Processors., , , , , and . IEEE Comput. Archit. Lett., 8 (1): 17-20 (2009)Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , and . International Conference on Supercomputing, page 12-19. ACM, (1997)Runtime-assisted cache coherence deactivation in task parallel programs., , , , and . SC, page 35:1-35:12. IEEE / ACM, (2018)Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications., , , , and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 53-64. Springer, (2008)Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors., , and . IEEE Trans. Computers, 31 (12): 1227-1234 (1982)