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Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion., , , , , и . ISQED, стр. 144-149. IEEE, (2011)Network flow-based simultaneous retiming and slack budgeting for low power design., , , , , , и . ASP-DAC, стр. 473-478. IEEE, (2011)Floorplanning with abutment constraints based on corner block list., , , , , и . Integr., 31 (1): 65-77 (2001)Post-floorplanning power optimization for MSV-driven application specific NoC design., и . ISCAS, стр. 994-997. IEEE, (2014)Through-Silicon-Via assignment for 3D ICs., , , и . ASICON, стр. 353-356. IEEE, (2011)Corner block list representation and its application to floorplan optimization., , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 51-II (5): 228-233 (2004)Mixed-Crossing-Avoided Escape Routing of Mixed-Pattern Signals on Staggered-Pin-Array PCBs., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (4): 571-584 (2014)Stairway compaction using corner block list and its applications with rectilinear blocks., , , , , и . ACM Trans. Design Autom. Electr. Syst., 9 (2): 199-211 (2004)Integrated interlayer via planning and pin assignment for 3D ICs., , , и . SLIP, стр. 99-104. ACM, (2009)Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips., , , , и . ISCAS, стр. 1-4. IEEE, (2018)