( en | de | ru )

 

Disambiguation of "Ahsan, Ishtiaq"

Author of the publication

copydeleteadd this publication to your clipboard
In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory.

, , , , , , , , , , , , , , , , , and . CoRR, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ahsanullah

Ishtiaq Ahmed

Muhammad Ahsan

Nasir Ahsan

Ahsan Abdullah

 

Other publications of authors with the same name

A Simplified Yield Model for SRAM Repair in Advanced Technology., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (11): 2494-2503 (2018)In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory., , , , , , , , , and 8 other author(s). CoRR, (2022)A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference., , , , , , , , , and 19 other author(s). CoRR, (2022)Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited)., , , , , , , , , and 15 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing., , , , , , , , , and 14 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)HERMES-Core - A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 57 (4): 1027-1038 (2022)An analog-AI chip for energy-efficient speech recognition and transcription., , , , , , , , , and 14 other author(s). Nat., 620 (7975): 768-775 (2023)