( en | de | ru )

 

Disambiguation of "Lee, Kyung-Hoon"

Author of the publication

copydeleteadd this publication to your clipboard
A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET.

, , , , , , , , , , and . VLSI Technology and Circuits, page 172-173. IEEE, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kyung Hoon Hwang

Kyung-Hoon Min

Chul-Hoon Lee

Jae-Hoon Lee

Song Hoon Lee

 

Other publications of authors with the same name

Timing synchronization method for device-to-device communication system., , and . ICUIMC, page 105. ACM, (2013)A fine timing synchronization method on group communication system enablers for LTE., , and . APCC, page 21-25. IEEE, (2013)A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 µm CMOS A/D Converter for 3G Communication Systems., , , and . IEICE Trans. Electron., 92-C (9): 1194-1200 (2009)Communication quality of voice over TCP used for firewall traversal., , and . ICME, page 29-32. IEEE Computer Society, (2008)Fast recursive algorithms for morphological operators based on the basis matrix representation., , and . IEEE Trans. Image Processing, 5 (6): 1073-1077 (1996)A fast implementation algorithm and a bit-serial realization method for grayscale morphological opening and closing., , and . IEEE Trans. Signal Process., 43 (12): 3058-3061 (1995)Implementation of Local Boundary Conditions in Two ADI-FDTD Updating Schemes., , , , and . IEICE Trans. Commun., 90-B (5): 1286-1289 (2007)A comprehensive study on the prediction reliability of graph neural networks for virtual screening., , and . CoRR, (2020)Comprehensive Study on Molecular Supervised Learning with Graph Neural Networks., , , , , , , and . J. Chem. Inf. Model., 60 (12): 5936-5945 (2020)A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 172-173. IEEE, (2022)