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Steven P. Levitan (1950-2016)., and . IEEE Des. Test, 33 (3): 142-143 (2016)Managing Leakage Energy in Cache Hierarchies., , , , , , and . J. Instruction-Level Parallelism, (2003)A clock power model to evaluate impact of architectural and technology optimizations., , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (6): 844-855 (2002)The design and implementation of the Arithmetic Cube II, a VLSI signal processing system., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 1 (4): 491-502 (1993)The design of the MGAP-2: a micro-grained massively parallel array., , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (6): 709-716 (2000)Design considerations for databus charge recovery., , , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (1): 104-106 (2001)On the Effects of Process Variation in Network-on-Chip Architectures., , , , , , and . IEEE Trans. Dependable Secur. Comput., 7 (3): 240-254 (2010)Exploiting communication complexity for multilevel logic synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (10): 1017-1027 (1990)Efficiently computing communication complexity for multilevel logic synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (5): 545-554 (1992)A hybrid NoC design for cache coherence optimization for chip multiprocessors., , , , , and . DAC, page 834-842. ACM, (2012)