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3D-SWIFT: a high-performance 3D-stacked wide IO DRAM., , , , and . ACM Great Lakes Symposium on VLSI, page 51-56. ACM, (2014)Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (11): 1621-1624 (2010)E-Booster: A Field-Programmable Gate Array-Based Accelerator for Secure Tree Boosting Using Additively Homomorphic Encryption., , , , , , , , , and 4 other author(s). IEEE Micro, 43 (5): 88-96 (September 2023)Image captioning via hierarchical attention mechanism and policy gradient optimization., , , , , and . Signal Process., (2020)Satisfaction-aware Task Assignment in Spatial Crowdsourcing., , , , , and . Inf. Sci., (April 2023)Π-RT: A Runtime Framework to Enable Energy-Efficient Real-Time Robotic Vision Applications on Heterogeneous Architectures., , , , , and . Computer, 54 (4): 14-25 (2021)DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (8): 1586-1599 (2021)H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 4782-4796 (2022)Tensor train decomposition for solving large-scale linear equations., , , , , , and . Neurocomputing, (2021)NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs., , , , , and . IEEE Comput. Archit. Lett., 18 (1): 38-42 (2019)