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Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design.

, , , , and . ACM Trans. Design Autom. Electr. Syst., 24 (4): 42:1-42:19 (2019)

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Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1497-1505 (2017)Diagnostic simulation of stuck-at faults in combinational circuits., , and . J. Electron. Test., 8 (1): 87-97 (1996)Diagnosis meets Physical Failure Analysis: What is needed to succeed?. ITC, page 1442. IEEE Computer Society, (2004)Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure., , , and . ITC, page 1-9. IEEE, (2017)Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults., , and . VTS, page 1-6. IEEE, (2019)Simulation- and Deduction-Based Techniques for Fault Diagnosis. University of Illinois Urbana-Champaign, USA, (1997)Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection., , and . ITC, page 489-497. IEEE Computer Society, (2004)Diagnostic Simulation of Sequential Circuits Using Fault Sampling., , and . VLSI Design, page 476-481. IEEE Computer Society, (1998)Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs., , , and . DATE, page 996-1001. IEEE Computer Society, (2005)Fault Diagnosis and Fault Model Aliasing., , and . ISVLSI, page 206-211. IEEE Computer Society, (2005)