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Disambiguation of "Ren, Qiwei"

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Low Overhead Pilot Design for Channel Estimation in MIMO-OTFS Systems.

, , , and . ICCC Workshops, page 1-6. IEEE, (2023)

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Qiwei Jin

Zhongliang Ren

Jianxin Ren

Hongming Ren

Ling Ren

 

Other publications of authors with the same name

Hf0.5Zr0.5O2 1T-1C FeRAM arrays with excellent endurance performance for embedded memory., , , , , , , , and . Sci. China Inf. Sci., (April 2023)Logic-DRAM Co-Design to Exploit the Efficient Repair Technique for Stacked DRAM., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (5): 1362-1371 (2015)A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power., , , , , , , , , and 1 other author(s). ASICON, page 426-428. IEEE, (2017)A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV., , , , , , , , , and 8 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (1): 128-141 (2023)184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System., , , , , , , , , and 9 other author(s). ISSCC, page 1-3. IEEE, (2022)A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement., , , , , , , , , and 15 other author(s). CICC, page 1-4. IEEE, (2017)A 1596GB/s 48Gb Embedded DRAM 384-Core SoC with Hybrid Bonding Integration., , , , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)Low Overhead Pilot Design for Channel Estimation in MIMO-OTFS Systems., , , and . ICCC Workshops, page 1-6. IEEE, (2023)