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A methodology for formal design of hardware control with application to cache coherence protocols.

, , , , , and . DAC, page 724-729. ACM, (2000)

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Resurrecting infeasible clock-gating functions., , and . DAC, page 160-165. ACM, (2009)A topological characterization of weakness., , and . PODC, page 1-8. ACM, (2005)Reasoning with Temporal Logic on Truncated Paths., , , , , and . CAV, volume 2725 of Lecture Notes in Computer Science, page 27-39. Springer, (2003)Structural Contradictions., and . Haifa Verification Conference, volume 5394 of Lecture Notes in Computer Science, page 164-178. Springer, (2008)Safety and Liveness, Weakness and Strength, and the Underlying Topological Relations., , and . ACM Trans. Comput. Log., 15 (2): 13:1-13:44 (2014)Model checking the garbage collection mechanism of SMV.. Workshop on Software Model Checking @ CAV, volume 55 of Electronic Notes in Theoretical Computer Science, page 289-303. Elsevier, (2001)Functional Verification of Power Gated Designs by Compositional Reasoning., , and . CAV, volume 5123 of Lecture Notes in Computer Science, page 433-445. Springer, (2008)A methodology for formal design of hardware control with application to cache coherence protocols., , , , , and . DAC, page 724-729. ACM, (2000)A Practical Introduction to PSL, and . Series on Integrated Circuits and Systems Springer, (2006)Functional verification of power gated designs by compositional reasoning., , and . Formal Methods Syst. Des., 35 (1): 40-55 (2009)