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Fault Detection of Combinational Circuits Based on Supply Current., , , и . ITC, стр. 374-380. IEEE Computer Society, (1988)A built-in test circuit for open defects at interconnects between dies in 3D ICs., , , , и . 3DIC, стр. 1-5. IEEE, (2011)Efficient test length reduction techniques for interposer-based 2.5D ICs., , , , и . VLSI-DAT, стр. 1-4. IEEE, (2014)Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs., , , и . IEEE Trans. Computers, 64 (5): 1230-1240 (2015)On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan., , , и . IEICE Trans. Inf. Syst., 96-D (9): 1986-1993 (2013)Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits., , и . IEICE Trans. Inf. Syst., 87-D (3): 571-579 (2004)Current Testable Design of Resistor String DACs., , , , и . ATS, стр. 399-403. IEEE, (2007)Identification of Feedback Bridging Faults with Oscillation., , и . Asian Test Symposium, стр. 25-. IEEE Computer Society, (1999)Practical Fault Coverage of Supply Current Tests for Bipolar ICs., , , и . DELTA, стр. 189-194. IEEE Computer Society, (2004)On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure., , , , и . DELTA, стр. 269-274. IEEE Computer Society, (2004)