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Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution.

, , and . Integr., (2018)

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Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design., , , and . IEEE Trans. Computers, 67 (4): 528-542 (2018)An Area and Power Efficient Dynamic TDMA Based Photonic Network on Chip., , , , and . ISED, page 113-117. IEEE Computer Society, (2013)Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design., and . Integr., (2017)Deadline and energy aware dynamic task mapping and scheduling for Network-on-Chip based multi-core platform., , , and . J. Syst. Archit., (2017)A strategy for fault tolerant reconfigurable Network-on-Chip design., , and . VDAT, page 1-2. IEEE, (2016)Thermal-aware detour routing in 3D NoCs., , and . J. Parallel Distributed Comput., (2020)A Photonic Network on Chip with CDMA Links., , , , and . VDAT, volume 7373 of Lecture Notes in Computer Science, page 377-378. Springer, (2012)Design of an NoC with on-chip photonic interconnects using adaptive CDMA links., , , , and . SoCC, page 352-357. IEEE, (2012)An ILP-based floorplan-aware path synthesis technique for Application-Specific NoC design., and . RAIT, page 543-548. IEEE, (2016)Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution., , and . Integr., (2018)