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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

A. Rovinski, C. Zhao, K. Al-Hawaj, P. Gao, S. Xie, C. Torng, S. Davidson, A. Amarnath, L. Vega, B. Veluri, A. Rao, T. Ajayi, J. Puscar, S. Dai, R. Zhao, D. Richmond, Z. Zhang, I. Galton, C. Batten, M. Taylor, and R. Dreslinski. VLSI Circuits, page 30-. IEEE, (2019)

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Christopher Christopher

Christopher Georgi

Christopher Künzel

Christopher Schumacher

Christopher Huth

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AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.K. Koul, J. Melchert, K. Sreedhar, L. Truong, G. Nyengele, K. Zhang, Q. Liu, J. Setter, P. Chen, Y. Mei and 23 other author(s). ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (March 2023)Fast Extended GCD Calculation for Large Integers for Verifiable Delay Functions.K. Sreedhar, M. Horowitz, and C. Torng. IACR Cryptol. ePrint Arch., (2021)Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays.J. Melchert, K. Zhang, Y. Mei, M. Horowitz, C. Torng, and P. Raina. CoRR, (2022)Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays.J. Melchert, K. Zhang, Y. Mei, M. Horowitz, C. Torng, and P. Raina. IEEE Comput. Archit. Lett., 22 (1): 45-48 (January 2023)Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration.K. Feng, A. Carsello, T. Kong, K. Koul, Q. Liu, J. Melchert, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 13 other author(s). HCS, page 1-30. IEEE, (2022)Ultra-Elastic CGRAs for Irregular Loop Specialization.C. Torng, P. Pan, Y. Ou, C. Tan, and C. Batten. HPCA, page 412-425. IEEE, (2021)Creating an Agile Hardware Design Flow.R. Bahr, C. Barrett, N. Bhagdikar, A. Carsello, R. Daly, C. Donovick, D. Durst, K. Fatahalian, K. Feng, P. Hanrahan and 22 other author(s). DAC, page 1-6. IEEE, (2020)Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.K. Feng, T. Kong, K. Koul, J. Melchert, A. Carsello, Q. Liu, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 12 other author(s). IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains.A. Nayak, K. Zhang, R. Setaluri, A. Carsello, M. Mann, C. Torng, S. Richardson, R. Bahr, P. Hanrahan, M. Horowitz and 1 other author(s). ACM Trans. Reconfigurable Technol. Syst., 16 (2): 26:1-26:28 (June 2023)Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.A. Carsello, K. Feng, T. Kong, K. Koul, Q. Liu, J. Melchert, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 13 other author(s). VLSI Technology and Circuits, page 70-71. IEEE, (2022)

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Disambiguation of "Torng, Christopher"

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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

Please choose a person to relate this publication to

Christopher Christopher

Christopher Georgi

Christopher Künzel

Christopher Schumacher

Christopher Huth

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Torng, Christopher"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

Please choose a person to relate this publication to

Christopher Christopher

Christopher Georgi

Christopher Künzel

Christopher Schumacher

Christopher Huth

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.