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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

A. Rovinski, C. Zhao, K. Al-Hawaj, P. Gao, S. Xie, C. Torng, S. Davidson, A. Amarnath, L. Vega, B. Veluri, A. Rao, T. Ajayi, J. Puscar, S. Dai, R. Zhao, D. Richmond, Z. Zhang, I. Galton, C. Batten, M. Taylor, and R. Dreslinski. VLSI Circuits, page 30-. IEEE, (2019)

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Zhigang Gao

Gao Guo

Yi Gao

Yawen Gao

Hailong Gao

Other publications of authors with the same name

The BlackParrot BedRock Cache Coherence System.M. Wyse, D. Petrisko, F. Gilani, Y. Chueh, P. Gao, D. Jung, S. Muralitharan, S. Ranga, M. Oskin, and M. Taylor. CoRR, (2022)NoC Symbiosis : (Special Session Paper).D. Petrisko, C. Zhao, S. Davidson, P. Gao, D. Richmond, and M. Taylor. NOCS, page 1-8. IEEE, (2020)A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.S. Pal, D. Park, S. Feng, P. Gao, J. Tan, A. Rovinski, S. Xie, C. Zhao, A. Amarnath, T. Wesley and 8 other author(s). VLSI Circuits, page 150-. IEEE, (2019)The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.S. Davidson, S. Xie, C. Torng, K. Al-Hawaj, A. Rovinski, T. Ajayi, L. Vega, C. Zhao, R. Zhao, S. Dai and 10 other author(s). IEEE Micro, 38 (2): 30-41 (2018)A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.A. Rovinski, C. Zhao, K. Al-Hawaj, P. Gao, S. Xie, C. Torng, S. Davidson, A. Amarnath, L. Vega, B. Veluri and 11 other author(s). VLSI Circuits, page 30-. IEEE, (2019)A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.D. Park, S. Pal, S. Feng, P. Gao, J. Tan, A. Rovinski, S. Xie, C. Zhao, A. Amarnath, T. Wesley and 8 other author(s). IEEE J. Solid State Circuits, 55 (4): 933-944 (2020)BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs.D. Petrisko, F. Gilani, M. Wyse, D. Jung, S. Davidson, P. Gao, C. Zhao, Z. Azad, S. Canakci, B. Veluri and 4 other author(s). IEEE Micro, 40 (4): 93-102 (2020)COVID-19 Smart Chatbot Prototype for Patient Monitoring.H. Lei, W. Lu, A. Ji, E. Bertram, P. Gao, X. Jiang, and A. Barman. CoRR, (2021)

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Disambiguation of "Gao, Paul"

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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

Please choose a person to relate this publication to

Zhigang Gao

Gao Guo

Yi Gao

Yawen Gao

Hailong Gao

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Gao, Paul"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

Please choose a person to relate this publication to

Zhigang Gao

Gao Guo

Yi Gao

Yawen Gao

Hailong Gao

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.