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FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge.

W. Tang, M. Lee, J. Wu, Y. Xu, Y. Yu, Y. Liu, K. Ni, Y. Wang, H. Yang, V. Narayanan, and X. Li. IEEE Trans. Circuits Syst. I Regul. Pap., 70 (6): 2398-2411 (2023)

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Jinglan Wu

Recovery of citric acid from fermentation broth using simulated moving bed technology: = Reinigung von Zitronensäure aus Fermentationslösung durch kontinuierliche ChromatographieJ. Wu. Uni Erlangen-Nürnberg, (2009)

Changzhu Wu

Jinjin Wu

Yinghua Wu

Haiyan Wu

Other publications of authors with the same name

Victor: A Variation-resilient Approach Using Cell-Clustered Charge-domain computing for High-density High-throughput MLC CiM.M. Lee, W. Tang, Y. Chen, J. Wu, H. Zhong, Y. Xu, Y. Liu, H. Yang, V. Narayanan, and X. Li. DAC, page 1-6. IEEE, (2023)Design of Almost-Nonvolatile Embedded DRAM Using Nanoelectromechanical Relay Devices.H. Zhong, M. Gu, J. Wu, H. Yang, and X. Li. DATE, page 1223-1228. IEEE, (2020)Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices.J. Wu, T. Liao, T. Li, Y. Xu, V. Narayanan, Y. Liu, H. Yang, and X. Li. ICCAD, page 1-9. IEEE, (2023)Machine Learning for Electronic Design Automation: A Survey.G. Huang, J. Hu, Y. He, J. Liu, M. Ma, Z. Shen, J. Wu, Y. Xu, H. Zhang, K. Zhong and 6 other author(s). CoRR, (2021)FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge.W. Tang, M. Lee, J. Wu, Y. Xu, Y. Yu, Y. Liu, K. Ni, Y. Wang, H. Yang, V. Narayanan and 1 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 70 (6): 2398-2411 (2023)FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface.M. Lee, W. Tang, B. Xue, J. Wu, M. Ma, Y. Wang, Y. Liu, D. Fan, V. Narayanan, H. Yang and 1 other author(s). ISLPED, page 127-132. ACM, (2020)Enabling Lower-Power Charge-Domain Nonvolatile In-Memory Computing with Ferroelectric FETs.G. Yin, Y. Cai, J. Wu, Z. Duan, Z. Zhu, Y. Liu, Y. Wang, H. Yang, and X. Li. CoRR, (2021)Exploiting FeFET Switching Stochasticity for Low-Power Reconfigurable Physical Unclonable Function.X. Guo, X. Ma, F. Müller, R. Olivo, J. Wu, K. Ni, T. Kämpfe, Y. Liu, H. Yang, and X. Li. ESSCIRC, page 119-122. IEEE, (2021)Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET Memory.J. Wu, Y. Xu, B. Xue, Y. Wang, Y. Liu, H. Yang, and X. Li. ASP-DAC, page 407-413. IEEE, (2020)Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs.X. Li, J. Wu, K. Ni, S. George, K. Ma, J. Sampson, S. Gupta, Y. Liu, H. Yang, S. Datta and 1 other author(s). IEEE Des. Test, 36 (3): 39-45 (2019)

BibSonomy

Disambiguation of "Wu, Juejian"

Please choose a person to relate this publication to

Jinglan Wu

Changzhu Wu

Jinjin Wu

Yinghua Wu

Haiyan Wu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wu, Juejian"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge.

Please choose a person to relate this publication to

Jinglan Wu

Changzhu Wu

Jinjin Wu

Yinghua Wu

Haiyan Wu

Other publications of authors with the same name

Disambiguation