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Disambiguation of "Jain, Pulkit"

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A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM.

, , and . ISLPED, page 119-120. ACM, (2009)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Pulkit Grover

Gora Jain

Arpit Jain

Rajiv Jain

Prabhat Jain

 

Other publications of authors with the same name

The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (2): 280-291 (2015)A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies., , , and . ISSCC, page 506-507. IEEE, (2011)Logic-compatible embedded DRAM design for memory intensive low power systems., , and . ISCAS, page 277-280. IEEE, (2010)A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches., , , and . IEEE J. Solid State Circuits, 47 (2): 547-559 (2012)Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design., , , , , and . IEEE Micro, 34 (6): 74-85 (2014)A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V., , , , , , , , , and 7 other author(s). ISSCC, page 212-214. IEEE, (2019)An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs., , and . ESSDERC, page 262-265. IEEE, (2012)Design and Implementation of a Quantitative Network Health Monitoring and Recovery System., , , , and . Wirel. Pers. Commun., 125 (1): 367-397 (2022)Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs., , , , and . VLSI Technology and Circuits, page 112-113. IEEE, (2022)16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing., , , , , and . ISSCC, page 248-250. IEEE, (2021)