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Disambiguation of "Chun, Ki Chul"

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A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM.

, , and . ISLPED, page 119-120. ACM, (2009)

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Chul Chun

Ki-Chul Choi

Rajani Chulyadyo

Evgueni Chulkov

Chulaporn Kamnerdpetch

 

Other publications of authors with the same name

Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs., , and . IEEE J. Solid State Circuits, 39 (4): 694-703 (2004)A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme., , and . VLSIC, page 130-131. IEEE, (2012)A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process., , , , , , , , , and 37 other author(s). ISSCC, page 206-208. IEEE, (2018)A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor., , , and . IEEE J. Solid State Circuits, 47 (10): 2517-2526 (2012)A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme., , and . IEEE J. Solid State Circuits, 48 (5): 1302-1314 (2013)A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM., , and . ISLPED, page 119-120. ACM, (2009)A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches., , , and . IEEE J. Solid State Circuits, 46 (6): 1495-1505 (2011)A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applications., , and . CICC, page 1-4. IEEE, (2013)22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme., , , , , , , , , and 25 other author(s). ISSCC, page 330-332. IEEE, (2020)A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies., , , and . ISSCC, page 506-507. IEEE, (2011)