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Disambiguation of "Huang, Hongye"

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A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter.

, , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 59 (4): 993-1005 (April 2024)

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Haishi Huang

Feiqing Huang

Zhida Huang

Ying Huang

Haowei Huang

 

Other publications of authors with the same name

A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR., , , , , , , , , and 16 other author(s). IEEE J. Solid State Circuits, 55 (9): 2371-2386 (2020)A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 256-258. IEEE, (2019)A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation., , , , , , , , , and 15 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth., , , , , , , , , and 1 other author(s). ISSCC, page 454-456. IEEE, (2021)A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver., , , , , , , and . ESSCIRC, page 310-313. IEEE, (2018)A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 59 (4): 993-1005 (April 2024)A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch., , , , , , , , , and 2 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 68 (1): 196-209 (2021)A 265- $\mu$ W Fractional- $N$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 54 (12): 3478-3492 (2019)A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 53 (12): 3672-3687 (2018)A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path., , , , , , and . ESSCIRC, page 265-268. IEEE, (2023)