( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
An NS-SAR ADC with Full-bit High-order Mismatch Shaped CDAC.

, , , , , , и . ISCAS, стр. 1-5. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Xiyuan Bai

Xiyuan Liu

Xiyuan Liu

Tang Tang

Xiyuan Hu

 

Другие публикации лиц с тем же именем

A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 59 (3): 842-854 (марта 2024)A Two-Step ADC With a Continuous-Time SAR-Based First Stage., , , , , , , , , и . IEEE J. Solid State Circuits, 54 (12): 3375-3385 (2019)A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing., , , , и . A-SSCC, стр. 1-3. IEEE, (2021)16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation., , , , и . ISSCC, стр. 258-260. IEEE, (2020)A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation., , , , , , и . VLSI Circuits, стр. 1-2. IEEE, (2020)An NS-SAR ADC with Full-bit High-order Mismatch Shaped CDAC., , , , , , и . ISCAS, стр. 1-5. IEEE, (2023)A pipelined SAR ADC reusing the comparator as residue amplifier., , , , , и . CICC, стр. 1-4. IEEE, (2017)A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC., , , , , , , , , и . CICC, стр. 1-2. IEEE, (2023)A 0.004mm2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp., , , и . ISSCC, стр. 164-166. IEEE, (2022)S2-PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits., , и . ASP-DAC, стр. 268-273. ACM, (2019)