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Hardware Identification of Cache Conflict Misses.

, and . MICRO, page 126-135. ACM/IEEE Computer Society, (1999)

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Exploring the Potential of Architecture-Level Power Optimizations., and . PACS, volume 3164 of Lecture Notes in Computer Science, page 132-147. Springer, (2003)Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management., , and . IEEE Micro, 39 (3): 75-83 (2019)Heterogeneous Computing Guest editors' introduction., and . IEEE Micro, 35 (4): 4-5 (2015)Editorial: Special Section on CMP Architectures., and . IEEE Trans. Parallel Distributed Syst., 18 (8): 1025-1027 (2007)Symbiotic jobscheduling for a simultaneous multithreaded processor, and . SIGARCH Comput. Archit. News, 28 (5): 234--244 (November 2000)Mitigating Speculative Execution Attacks via Context-Sensitive Fencing., , and . IEEE Des. Test, 39 (4): 49-57 (2022)Fast switching of threads between cores., , , , and . ACM SIGOPS Oper. Syst. Rev., 43 (2): 35-45 (2009)Introduction., and . ACM Trans. Archit. Code Optim., 2 (1): 1-2 (2005)Packet Chasing: Spying on Network Packets over a Cache Side-Channel., , and . ISCA, page 721-734. IEEE, (2020)Deciphering Predictive Schedulers for Heterogeneous-ISA Multicore Architectures., , and . PMAM@PPoPP, page 51-60. ACM, (2019)