Author of the publication

A test circuit for pin shorts generating oscillation in CMOS logic circuits.

, , , and . Syst. Comput. Jpn., 35 (13): 10-20 (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan., , , and . IEICE Trans. Inf. Syst., 96-D (9): 1986-1993 (2013)Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits., , and . IEICE Trans. Inf. Syst., 87-D (3): 571-579 (2004)A built-in test circuit for open defects at interconnects between dies in 3D ICs., , , , and . 3DIC, page 1-5. IEEE, (2011)Efficient test length reduction techniques for interposer-based 2.5D ICs., , , , and . VLSI-DAT, page 1-4. IEEE, (2014)Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs., , , and . IEEE Trans. Computers, 64 (5): 1230-1240 (2015)Fault Detection of Combinational Circuits Based on Supply Current., , , and . ITC, page 374-380. IEEE Computer Society, (1988)Current Testable Design of Resistor String DACs., , , , and . ATS, page 399-403. IEEE, (2007)Identification of Feedback Bridging Faults with Oscillation., , and . Asian Test Symposium, page 25-. IEEE Computer Society, (1999)Test Time Reduction for I DDQ Testing by Arranging Test Vectors., , and . Asian Test Symposium, page 423-428. IEEE Computer Society, (2002)Reducing Scan Shifts Using Folding Scan Trees., , , , and . Asian Test Symposium, page 6-11. IEEE Computer Society, (2003)