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Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles.

J. Lin, Y. Deng, S. Li, B. Yu, L. Chang, и T. Peng. IEEE Trans. Very Large Scale Integr. Syst., 27 (1): 57-68 (2019)

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Ming Lin

Ming-Yih Lin

Ming-hsin Lin

Ming Kuan Lin

Ming-Lang Lin

Другие публикации лиц с тем же именем

Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs.J. Lin, C. Huang, и J. Yang. DATE, стр. 1339-1344. IEEE, (2018)Placement with symmetry constraints for analog layout design using TCG-S.J. Lin, G. Wu, Y. Chang, и J. Chuang. ASP-DAC, стр. 1135-1137. ACM Press, (2005)Voltage island-driven floorplanning considering level shifter placement.J. Lin, W. Cheng, C. Lee, и R. Hsu. ASP-DAC, стр. 443-448. IEEE, (2012)Placement Density Aware Power Switch Planning Methodology for Power Gating Designs.J. Lin, и C. Lin. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 766-777 (2015)Generic ILP-based approaches for time-multiplexed FPGA partitioning.G. Wu, J. Lin, и Y. Chang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (10): 1266-1274 (2001)Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC.J. Lin, W. Chang, H. Hsieh, Y. Shyu, Y. Chang, и J. Lu. IEEE Trans. Very Large Scale Integr. Syst., 29 (9): 1652-1664 (2021)A Systematic Design Methodology of Asynchronous SAR ADCs.C. Huang, J. Lin, Y. Shyu, и S. Chang. IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1835-1848 (2016)Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles.J. Lin, Y. Deng, S. Li, B. Yu, L. Chang, и T. Peng. IEEE Trans. Very Large Scale Integr. Syst., 27 (1): 57-68 (2019)Graph matching-based algorithms for array-based FPGA segmentation design and routing.J. Lin, S. Pan, и Y. Chang. ASP-DAC, стр. 851-854. ACM, (2003)Voltage-Drop Optimization Through Insertion of Extra Stripes to a Power Delivery Network.J. Lin, Y. Chen, Y. Kung, и H. Lin. ISPD, стр. 35-43. ACM, (2023)

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