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Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (12): 1414-1425 (2001)Hierarchical Error Diagnosis Targeting RTL Circuits., , , , and . VLSI Design, page 436-441. IEEE Computer Society, (2000)Low power chips: a fabless asic perspective., and . ISLPED, page 347-348. ACM, (2008)Cellular automata as a built in self test structure., , , , , and . ASP-DAC, page 319-324. ACM, (2001)Implementing the Best Processor Cores., , and . VLSI Design, page 17-18. IEEE Computer Society, (2008)A CAD Tool for Design of On-Chip Store & Generate Scheme., , and . VLSI Design, page 169-174. IEEE Computer Society, (1994)Delay Fault Test Generation with Cellular Automata., , , , and . VLSI Design, page 281-286. IEEE Computer Society, (1993)Modeling the unknown! Towards model-independent fault and error diagnosis., and . ITC, page 1094-1101. IEEE Computer Society, (1998)Partial Scan Design Based on State Transition Modeling., and . ITC, page 538-547. IEEE Computer Society, (1996)Fault dictionary compaction by output sequence removal., and . ICCAD, page 576-579. IEEE Computer Society / ACM, (1994)