( en | de | ru )

 

Disambiguation of "Cho, Young-Chul"

Author of the publication

copydeleteadd this publication to your clipboard
A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics.

, , , , , , , , , , , , , and . ESSCIRC, page 463-466. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Chul-Woong Cho

Hyun-Chul Cho

Young-Chul Chang

Young Geun Cho

Eun Young Cho

 

Other publications of authors with the same name

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 43 (1): 121-131 (2008)5.7 A 29nW bandgap reference circuit., , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)CDISC-compliant clinical trial imaging management system with automatic verification and data Transformation: Focusing on tumor response assessment data in clinical trials., , , , , , , , and . J. Biomed. Informatics, (2021)A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics., , , , , , , , , and 4 other author(s). ESSCIRC, page 463-466. IEEE, (2021)25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation., , , , , , , , , and 16 other author(s). ISSCC, page 430-431. IEEE, (2014)Gadoxetate-enhanced dynamic contrast-enhanced MRI for evaluation of liver function and liver fibrosis in preclinical trials., , , , , , , , and . BMC Medical Imaging, 19 (1): 89:1-89:9 (2019)An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion., , , , , , , , , and 19 other author(s). ISSCC, page 492-617. IEEE, (2007)A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme., , , , , , , , , and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)Accuracy evaluation of blood flow distribution in the Fontan circulation: effects of resolution and velocity noise., , , , , , , , , and 1 other author(s). J. Vis., 22 (2): 245-257 (2019)A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation., , , , , , , , , and 10 other author(s). IEEE J. Solid State Circuits, 50 (1): 178-190 (2015)