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Disambiguation of "Byun, Jindo"

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A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics.

, , , , , , , , , , , , , and . ESSCIRC, page 463-466. IEEE, (2021)

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Cheol-Woong Byun

Youngjin Byun

Sangwon Byun

Woo-Hyuk Byun

Tae-Gang Byun

 

Other publications of authors with the same name

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics., , , , , , , , , and 4 other author(s). ESSCIRC, page 463-466. IEEE, (2021)A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE., , , , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process., , , , , , , , , and 18 other author(s). CICC, page 1-2. IEEE, (2022)A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface., , , , , , , , , and 39 other author(s). ISSCC, page 216-218. IEEE, (2019)Signal Integrity Improvements of a MEMS Probe Card Using Back-Drilling and Equalizing Techniques., , , , , and . IEEE Trans. Instrumentation and Measurement, 60 (3): 872-879 (2011)A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application., , , , , , , , , and 13 other author(s). VLSI Technology and Circuits, page 148-149. IEEE, (2022)