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Disambiguation of "Alpert, Charles J."

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Techniques for Fast Physical Synthesis.

, , , , , , , , and . Proc. IEEE, 95 (3): 573-599 (2007)

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Günther Alpert

Christian Alpert

Hansgünther Alpert

Thomas Alpert

Charles von J Russ

 

Other publications of authors with the same name

GLARE: global and local wiring aware routability evaluation., , , , , , , , , and . DAC, page 768-773. ACM, (2012)Closed-form delay and slew metrics made easy., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (12): 1661-1669 (2004)Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (4): 509-516 (2004)Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths., , , , and . ASP-DAC, page 350-355. IEEE, (2013)Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique., , , , , , and . ISPD, page 104-109. ACM, (2002)Multilevel Circuit Partitioning., , and . DAC, page 530-533. ACM Press, (1997)A semi-persistent clustering technique for VLSI circuit placement., , , , and . ISPD, page 200-207. ACM, (2005)A fast algorithm for identifying good buffer insertion candidate locations., , and . ISPD, page 47-52. ACM, (2004)Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 726-739 (2015)Accurate estimation of global buffer delay within a floorplan., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 1140-1145 (2006)