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GLARE: global and local wiring aware routability evaluation., , , , , , , , , and . DAC, page 768-773. ACM, (2012)Challenges of cell selection algorithms in industrial high performance microprocessor designs., , and . Integr., (2016)Cell Selection for High-Performance Designs in an Industrial Design Flow., , and . ISPD, page 65-72. ACM, (2016)Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths., , , , and . ASP-DAC, page 350-355. IEEE, (2013)Grid-to-ports clock routing for high performance microprocessor designs., , , and . ISPD, page 21-28. ACM, (2011)ISPD 2010 high performance clock network synthesis contest: benchmark suite and results.. ISPD, page 143. ACM, (2010)Accurate estimation of global buffer delay within a floorplan., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 1140-1145 (2006)Postgrid Clock Routing for High Performance Microprocessor Designs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (2): 255-259 (2012)Porosity-aware buffered Steiner tree construction., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (4): 517-526 (2004)WRIP: logic restructuring techniques for wirelength-driven incremental placement., , , , and . ACM Great Lakes Symposium on VLSI, page 327-332. ACM, (2012)