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Disambiguation of "Heittmann, Arne"

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Correlation-based feature detection using pulsed neural networks.

, and . NNSP, page 479-488. IEEE, (2003)

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Arne Heittmann

Walter Arne

Friedrich Arnemann

Sabine Arnecke

Jan-Dirk Arneth

 

Other publications of authors with the same name

Correlation-based feature detection using pulsed neural networks., and . NNSP, page 479-488. IEEE, (2003)Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation., , , , and . Image Processing: Algorithms and Systems, volume 5298 of SPIE Proceedings, page 290-296. SPIE, (2004)Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity., , , , and . NNSP, page 657-666. IEEE, (2002)A hybrid CMOS/memristive nanoelectronic circuit for programming synaptic weights., and . ESANN, (2012)3D Chip Stack Technology Using Through-Chip Interconnects., , , , , , , , and . IEEE Des. Test Comput., 22 (6): 512-518 (2005)Memristor-based hardware and algorithms for higher-order Hopfield optimization solver outperforming quadratic Ising machines., , , , , , , , and . CoRR, (2023)Pulse coupled neural networks with adaptive synapses for image segmentation., , , , and . ARCS Workshops, volume P-41 of LNI, page 275-282. GI, (2004)Mixing circuit based on neural associative memories and nanoelectronic 1S1R cells., and . NANOARCH, page 119-124. IEEE, (2017)Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuits., and . ACM Great Lakes Symposium on VLSI, page 227-232. ACM, (2012)Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells., and . DATE, page 1496-1499. IEEE, (2018)