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Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks.

, , and . ITC, page 887-896. IEEE Computer Society, (1991)

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Verification of Embedded Memory Systems using Efficient Memory Modeling, , and . CoRR, (2007)An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking., , and . VLSI Design, 10 (3): 249-263 (2000)Efficient SAT-based bounded model checking for software verification., , , , and . Theor. Comput. Sci., 404 (3): 256-274 (2008)Exploiting Retiming in a Guided Simulation Based Validation Methodology., , and . CHARME, volume 1703 of Lecture Notes in Computer Science, page 350-353. Springer, (1999)Efficient distributed SAT and SAT-based distributed Bounded Model Checking., , , and . Int. J. Softw. Tools Technol. Transf., 8 (4-5): 387-396 (2006)Verification of Embedded Memory Systems using Efficient Memory Modeling., , and . DATE, page 1096-1101. IEEE Computer Society, (2005)Property-specific witness graph generation for guided simulation., , , , , and . DATE, page 799. IEEE Computer Society, (2001)Technology Mapping for Lower Power., , and . DAC, page 74-79. ACM Press, (1993)Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs., , , , and . ICCAD, page 286-292. IEEE Computer Society, (2001)Scheduling Techniques to Enable Power Management., , , and . DAC, page 349-352. ACM Press, (1996)